Digital
• Clocks: Internal.SPDIF In
• Low Jitter Design: < 1 ns in PLL mode, all inputs
• Internal clock: < 800 ps Jitter Random Spread Spectrum
• Jitter suppression of external clocks: > 50 dB (2.4 kHz)
• Effective clock jitter influence on DA conversion: nearzero
• PLL ensures zero dropout, even at more than 100 ns jitter
• Additional Digital Bitclock PLL for trouble-free varispeed ADAT operation
• Supported sample rates for external clocks: 28 kHz up to 200 kHz
• Internally supported sample rates: 44.1 kHz up to 768 kHz

Low Jitter Design: < 1 ns in PLL mode, all inputs
ns？Not ps?
Internal clock: < 800 ps Jitter Random Spread Spectrum
Not fs？

“With SteadyClock FS the focus was put on reducing the self jitter of SteadyClock to new lows, by improving its second, analog PLL circuit, and referencing both Direct Digital Synthesis and PLL to a low phase noise quartz crystal. The self jitter measured through DA conversion now reaches levels that usually are only available in master quartz clock mode, while SteadyClock still always runs in PLL mode - no matter if internal or external clock, sound is exactly the same (again). The low phase noise oscillator driving the updated circuit reaches jitter specs lower than a picosecond (ps), an area called FemtoSecond. Hence SteadyClock FS.”