Thanks, hard to make out brand or any other info though.

But isn't 25 mhz a strange frequency for a DAC clock? How do you generate accurate 44.1/48 khz and multiples from 25 mhz?

as I said the oscillator work with the FPGA on the right, and together they form a PLL. RME market this as their SteadyClock FS technology. With PLL, you get whatever frequency you want with super high accuracy (as long as the low frequency clock, 25mhz here, is accurate).

The 25mhz clock is not meant to be a clock signal to control AD/DA chip. Rather it acts as a error correction for a much higher frequency but unstable clock (up to GHz) for the FPGA. So the FPGA will now have an accurate GHz clock after the correction. so it can create multiple accurate clocks for anything with much lower frequencies (such as 44.1khz)

This is a much better/cheaper clock source than multiples of 44.1/48. Their FPGA can create multiple PLLs with this 25mhz clock. For instance one for DA/AD chips, the other to correct SRC input signal, etc.  The latter (in ADI-2 Pro, it's whatever clock the SRC chips accepts, that is, 28-200khz) may not be a 44.1/48 multiple --- you just cannot do that with traditional technologies.

Google PLL to learn more.

Hi, a little late, and a slightly off topic question:
The HDSP 9632 has a 50Mhz clock, which, by it's age, is certainly not "femto". Is it, frequency wyse, possible, thanks to PLL, to replace this inbuild oscillator by a more modern and ultra-low-jitter oscillator, but which may oscillate at a more easily obtainable 49.152MHz? Or must this oscillator output 50Mhz and nothing else?