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Topic: Steadyclock versions in Madiface / PRO / XT

Hello,

Do all the current madifaces have the latest steadyclock or does it vary with the models?

2 (edited by ramses 2021-02-08 18:09:56)

Re: Steadyclock versions in Madiface / PRO / XT

From manuals:

https://www.rme-audio.de/download/mface_pro_d.pdf
https://www.rme-audio.de/download/mface_pro_e.pdf

MADIface Pro
25.3 Digital
• Clocks: Internal, MADI In
• Low Jitter Design: < 1 ns in PLL mode, all inputs
• Internal clock: 800 ps Jitter, Random Spread Spectrum
• Jitter suppression of external clocks: > 50 dB (2.4 kHz)
• Effective clock jitter influence on AD and DA conversion: near zero
• PLL ensures zero dropout, even at more than 100 ns jitter
• Supported sample rates: 28 kHz up to 200 kHz

https://www.rme-audio.de/download/madiface_xt_d.pdf
https://www.rme-audio.de/download/madiface_xt_e.pdf

MADIface XT
29.4 Digital
• Clocks: Internal, MADI In, Word Clock In, AES In
• Low jitter design: < 1 ns in PLL mode, all inputs
• Internal clock: 800 ps jitter, random spread spectrum
• Jitter suppression of external clocks: about 30 dB (2.4 kHz)
• Effective clock jitter influence on DA conversion: near zero
• Provides nearly jitter-free word clock directly from the MADI input signal
• Input PLL ensures zero dropout, even at more than 100 ns jitter
• Supported sample rates: 28 kHz up to 200 kHz

See also these useful videos:
EN https://www.youtube.com/watch?v=Ti0aHW- … e=emb_logo
DE https://www.youtube.com/watch?v=6rcBVuW … e=emb_logo

BR
Ramses
X10SRi-F, E5-1650v4, Win10Pro20H2, Cub11Pro, UFX+ (v0.9735), XTC, 12Mic, ADI-2 Pro FS R BE

3

Re: Steadyclock versions in Madiface / PRO / XT

So the Pro has a slightly better clock if im reading this correctly? XT and normal Madiface share the same, atleast according to the manuals.

4 (edited by ramses 2021-02-08 19:40:10)

Re: Steadyclock versions in Madiface / PRO / XT

I recommend to have a look at the videos.
MC tells you need to differentiate between interface jitter and sampling jitter.

Interface jitter, the jitter between interfaces (like AES, MADI, ..) is in the range of 1ns and according to MC uncritical.

In the second part MC compares the sampling jitter of different devices:
- without Steadyclock (with standard AKM SPDIF receiver and AK4490 chip)
- with Steadyclock
- with Steadyclock FS

The jittered signal is visible in the FFT as jitter modulated sidebands at 7.5 and 12.5 kHz (+/- 2.5 kHz from 10kHz)
The device without steadyclock (but with the AK4490 chip) has
- with 20n             jitter:       sidebands of -68dB                                  out of the noise floor of -130dB
- with 1ns             jitter:       sidebands of -94dB (this is ~CD quality)  out of the noise floor of -130dB
- with only 100ps jitter: still sidebands of -114 dB                                out of the noise floor of -130dB

See the comment at 09:43: This is the FFT's noise floor. The overall noise floor is much higher.
These sidebands are measurable but not audible within the noise.

Starting with 09:56 in the video Matthias Carstens shows values of the Fireface UC. This is a device with steadyclock which has been designed in 2009 (with an older AD/DA converter compared to modern units). Its not on the level of an AK4490, but you can see an intersting thing.

The older UC with Steadyclock provides a lower noise floor of -140dB compared to the device with more modern AK4490 converter (-130dB) but without Steadyclock. So the UC with older converter doesn't reach the level of the AK4490 but provides a better analog and clock implementation with lower noise floor.

The UC with steadyclock provides:
- with 20ns             jitter:       sidebands of -119dB                                  out of the noise floor of -140dB

So when you compare the UC and the device without steadyclock (but AK4490) at 20ns jitter, then the UC reduces the jitter from -68 to -119dB = 51dB Jitter Reduction. RME always advertized only 30dB reduction, but you can see its more.

Steadyclock is being advertized to have an even higher jitter reduction and less self jitter.
ADI-2 DAC
- without jitter: noise floor of -155dB
- with   50ns digital jitter: noise floor of -155 dB (same, no side bands!!!)
- with 100ns digital jitter: noise floor of -155 dB (same, no side bands!!!) <- high jitter ("artifical" value!)
- with 150ns digital jitter: noise floor of -155 dB (same, no side bands!!!) <- ridiculous high jitter ("artifical" value!)

My personal conclusions from watching (and slowly "digesting" this information):
1. steadyclock implementation of the UC (design of 2009) lowers the noisefloor significantly
2. even with 20ns jitter sidebands are at a very low value of -119dB
3. the jitter reduction is much higher compared to a device without steadyclock (but modern AK4490 converter)
4. Steadyclock FS eliminates jitter completely even at ridiculous high "artificial" jitter values of 150ns.

So I think that you do not need to worry much when choosing a RME device, what Steadyclock version is implemented.
Steadyclock does very fine no matter whether your RME device has "Steadyclock" or "Steadyclock FS".

And if you simply want SteadyClock FS, then integrate it into your setup like I described here: https://www.tonstudio-forum.de/blog/ind … our-Setup/. By this you get a real wonderful monitor and phones preamp.

P.S.: I hope I interpreted the information and values shown in both RME videos correctly, sorry if there should be a mistake. I posted this: a) to "slowly digest" this information for myself, b) as a little time saver whats the message of this.

BR
Ramses
X10SRi-F, E5-1650v4, Win10Pro20H2, Cub11Pro, UFX+ (v0.9735), XTC, 12Mic, ADI-2 Pro FS R BE