1 (edited by robpap 2022-10-04 15:11:28)

Topic: Feature request: memory-aligned buffers for ASIO driver (hdsp32.exe)

The support staff told me to post my message here for the RME developers:

When my C++ ASIO host is calling ASIOCreateBuffers(), I noticed that the Hammerfall DSP ASIO driver (for my HDPSe AES PCIe card) allocates buffers whose starting memory address is aligned to 16 bytes (the default).

It would be great to have them *aligned to 64 bytes* (the cacheline size) for the following reasons.

  • First, it is backward compatible, as 64-alignment is also a 16-alignment, so ASIO hosts using the16-aligned buffers still work.

  • Second, cache performance improves on small buffers. For example, using 32 samples in the Hammerfall DSP ASIO driver, each channel has a buffer size of 128 bytes. Due to the fact the buffers are 16-aligned, these 128 bytes are hosted in *three* consecutive cachelines, whereas 64-aligned buffers require *two* cachelines. In other words, one third of cacheline loads is automatically saved by ASIO hosts in this way (no change is needed in their code).

  • Third, some specialized AVX2 instructions that require 32-byte alignment could be used, whereas this is not possible now.

In summary, it would be very helpful if you could make this simple change in the next release of the Hammerfall DSP ASIO driver. Performance would have a benefit with no drawbacks (at least I could not see any of them so far).

Thank you
-R

Re: Feature request: memory-aligned buffers for ASIO driver (hdsp32.exe)

+1 if it will increase performance

Re: Feature request: memory-aligned buffers for ASIO driver (hdsp32.exe)

I have been contacted, thanks smile

Re: Feature request: memory-aligned buffers for ASIO driver (hdsp32.exe)

Any details?

Re: Feature request: memory-aligned buffers for ASIO driver (hdsp32.exe)

Yes curious too

Vincent, Amsterdam
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Babyface pro fs, HDSP9652+ADI-8AE, HDSP9632

Re: Feature request: memory-aligned buffers for ASIO driver (hdsp32.exe)

Sorry for the late answer. The developer did not get my point as thought it was the 4k system page, so I replied clarifying that it was the buffer alignment inside the page. But I never got a response after that.

As a matter of fact, also the latest release of the ASIO driver 4.40 has still the same issue: some AVX/AVX2 instructions that requires 32-byte alignment are not supported on the buffers.

The ASIO driver for USB Digiface supports them instead. Probably the developers' effort is currently more on the USB interfaces than PCIe interfaces (see the new Digiface AES).

In any case I am happy with the RME AES PCIe, but we are probably not exploiting the CPU full capabilities on it.